`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   17:41:58 10/22/2013
// Design Name:   timer
// Module Name:   /home/andy/Documents/uofa-mips/trunk/BoardSystem_trunk/nexys2_1200_audio_project/timer_test.v
// Project Name:  nexys2_1200_audio_project
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: timer
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module timer_test;

	// Inputs
	reg clk;
	reg reset;
	reg enable;
	reg [3:0] address;
	reg [31:0] dataIn;
	reg write;
	reg clk_to_count;

	// Outputs
	wire [31:0] dataOut;
	wire done;
	wire interrupt;

	// Instantiate the Unit Under Test (UUT)
	timer uut (
		.clk(clk), 
		.reset(reset), 
		.enable(enable), 
		.address(address), 
		.dataIn(dataIn), 
		.dataOut(dataOut), 
		.write(write), 
		.done(done), 
		.interrupt(interrupt), 
		.clk_to_count(clk_to_count)
	);
	
	initial begin
		// Initialize Inputs
		clk = 0;
		reset = 1;
		enable = 0;
		address = 0;
		dataIn = 0;
		write = 0;
		clk_to_count = 0;

		// Wait 100 ns for global reset to finish
		#40;
		
		reset = 0;
		write = 1;
		enable = 1;
		dataIn = 12'hfff;
		address = 13;
		
		#40;
		
		write = 0;
		enable = 1;
		
		#40;
		
		enable = 1;
		address = 0;
		dataIn = 30;
		write = 1;
		
		#20
		
		//address = 1;
		//dataIn = 29;
		//write = 1;
		//enable = 1;
		
		#20;
		
		address = 0;
		enable = 1;
		write = 0;
		
		#520;
		
		enable = 0;
		
		#160;
		
		enable = 1;
		address = 14;
		dataIn = 12'hfff;
		write = 0;
		
		# 40;
		  
		// Add stimulus here
		
	end
	
	
	always
	begin
		clk = 0;
		#10;
		clk = 1;
		#10;
	end
      
endmodule

